Karthikeyan Natarajan

Senior Software Engineer at NVIDIA · Austin, TX

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Austin, Texas

I am a Senior Software Engineer at NVIDIA, building GPU-accelerated data processing in CUDA: RAPIDS cuDF and the cuDF backend for the Velox query engine. From August 2014 to May 2019, I was a CAD DFT Engineer at NVIDIA, developing deep learning solutions for EDA problems, DFT algorithms, and applied parallel computing.

I did my M.S. (Research) at the Department of Electrical Engineering, Indian Institute of Technology Madras (IITM), where I worked on GPGPU parallel computing, VLSI CAD algorithms, FPGA implementations, and signal processing and communication algorithms.

My research interests include GPU-accelerated Databases, Data Processing, Parallel Computing (CUDA & Multi‑core), Machine Learning, Deep Learning, HW accelerators and EDA Algorithms.

News

Jul 08, 2026 NVIDIA Technical Blog (co-author): Running Low-Latency Analytical Workloads with GPU-Accelerated Presto on NVIDIA GB200 NVL72.
Jun 23, 2026 Paper Accelerating Presto with GPUs (with IBM Research) on arXiv; to appear at the VLDB 2026 ADMS workshop.
Apr 29, 2026 Talk at VeloxCon 2026 (Meta HQ, Menlo Park): NVIDIA’s work with Velox and HW acceleration.
Oct 07, 2025 IBM blog credits me among the NVIDIA contributors to cuDF-powered GPU execution in Velox: Accelerating data analytics with GPUs, Velox and NVIDIA.
Apr 15, 2025 Talk at VeloxCon 2025 (April 15–16, Meta HQ, Menlo Park): Accelerating Velox with RAPIDS cuDF.
Feb 20, 2025 NVIDIA Technical Blog: JSON Lines Reading with pandas 100x Faster Using NVIDIA cuDF.
Aug 23, 2024 Lightning talk at CppIndiaCon 2024 (August 23–24, online): SFINAE and its Uses.
Dec 15, 2023 NVIDIA Technical Blog: Streamline ETL Workflows with Nested Data Types in RAPIDS libcudf.
Feb 09, 2023 NVIDIA Technical Blog: GPU-Accelerated JSON Data Processing with RAPIDS.
Feb 07, 2023 US Patent US11574097B2 granted: Deep learning based identification of difficult to test nodes (NVIDIA).

Publications

Publications and patents in reverse chronological order.

See also my Google Scholar profile.

2026

  1. ADMS
    Accelerating Presto with GPUs
    Daniel Bauer, Luis Garcés-Erice, Deepak Majeti, Zoltán Arnold Nagy, Sean Rooney, Greg Kimball, Devavret Makkar, Todd Mostak, and Karthikeyan Natarajan
    In VLDB 2026 Workshop: Accelerating Analytics and Data Management Systems (ADMS), 2026
    arXiv HTML PDF

2019

  1. DAC
    High Performance Graph Convolutional Networks with Applications in Testability Analysis
    Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, Karthikeyan Natarajan, and Bei Yu
    In Proceedings of the 56th Annual Design Automation Conference (DAC), Jun 2019
    DOI HTML PDF

2018

  1. HiPC
    Lossless Parallel Implementation of a Turbo Decoder on GPU
    Karthikeyan Natarajan and Nitin Chandrachoodan
    In 2018 IEEE 25th International Conference on High Performance Computing (HiPC), Dec 2018
    DOI HTML PDF

2015

  1. NCC
    Non-uniform DFT implementation for channel simulations in GPU
    Karthikeyan Natarajan and Nitin Chandrachoodan
    In 2015 Twenty First National Conference on Communications (NCC), Feb 2015
    DOI HTML

2011

  1. ICDeCom
    A Novel Channel Estimation Technique for MIMO-OFDM Systems for Frequency Selective Rayleigh Channel
    N. Ashish, K. R. Atul Srivatsan, N. Karthikeyan, Srikar Gutta, Ashwini A. Raman, R. Ramanathan, and Ravi Teja Pasupuleti
    In 2011 International Conference on Devices and Communications (ICDeCom), Feb 2011
    DOI HTML
  2. ICETECT
    A Novel Channel Estimation Technique for MIMO-OFDM Systems for Frequency Selective Ricean Channel
    N. Ashish, K. R. Atul Srivatsan, N. Karthikeyan, Ravi Teja Pasupuleti, Srikar Gutta, Ashwini A. Raman, and R. Ramanathan
    In 2011 International Conference on Emerging Trends in Electrical and Computer Technology (ICETECT), Mar 2011
    DOI HTML

Patents

  1. US Patent
    Deep learning based identification of difficult to test nodes
    Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, and Sandeep Gangundi
    Feb 2023
    Granted February 7, 2023; divisional of US11010516B2
    HTML PDF
  2. US Patent
    Deep learning based identification of difficult to test nodes
    Harbinder Sikka, Kaushik Narayanun, Lijuan Luo, Karthikeyan Natarajan, Manjunatha Gowda, and Sandeep Gangundi
    May 2021
    Granted May 18, 2021
    HTML PDF
  3. US Patent
    Deep learning testability analysis with graph convolutional networks
    Yuzhe Ma, Haoxing Ren, Brucek Khailany, Harbinder Sikka, Lijuan Luo, and Karthikeyan Natarajan
    May 2020
    Granted May 19, 2020
    HTML PDF

Talks

Conference talks and GPU hackathon mentoring.

NVIDIA's work with Velox and HW acceleration (VeloxCon 2026)

NVIDIA's work with Velox and HW acceleration

VeloxCon 2026 · April 29, 2026 · Meta HQ, Menlo Park · Video

Accelerating Velox with RAPIDS cuDF (VeloxCon 2025)

Accelerating Velox with RAPIDS cuDF

VeloxCon 2025 · April 15–16, 2025 · Meta HQ, Menlo Park · Video

SFINAE and its Uses (CppIndiaCon 2024)

SFINAE and its Uses (lightning talk)

CppIndiaCon 2024 · August 23–24, 2024 · Online · Video

Mentoring

Sep 2021 NASA GPU Hackathon: primary GPU mentor for team BingoBros (nasa/bingo)
Aug 2021 C-DAC HPC Hackathon 2021: CUDA mentor
Sep 2018 C-DAC GPU Hackathon, Pune: CUDA mentor

Writing

Articles on the NVIDIA Technical Blog.

All my posts are on my NVIDIA Developer author page.

Jul 8, 2026 Running Low-Latency Analytical Workloads with GPU-Accelerated Presto on NVIDIA GB200 NVL72 (co-author)
Feb 20, 2025 JSON Lines Reading with pandas 100x Faster Using NVIDIA cuDF
Dec 15, 2023 Streamline ETL Workflows with Nested Data Types in RAPIDS libcudf
Feb 9, 2023 GPU-Accelerated JSON Data Processing with RAPIDS

Projects

Open-source GPU data processing work, and earlier projects in GPU computing, signal processing and FPGA design.

Open source

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cuDF

RAPIDS GPU DataFrame library. Top-15 all-time contributor (1,000+ commits): GPU JSON reader/writer, JIT & UDFs, groupby, reductions, nested types.
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Velox + cuDF

GPU execution backend for the Velox query engine (Presto, Spark) built on cuDF: GPU operators and device-compatible SQL functions. 32 merged PRs.

Earlier work

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NUDFT in GPU

Accelerated Non-Uniform Discrete Fourier Transform in CUDA.
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SVD in FPGA

Singular Value Decomposition in FPGA using the Jacobi iterative algorithm without multipliers.
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Lossless GPU Turbo decoder

Lossless parallel Turbo decoder in CUDA, 5x speedup. Published at IEEE HiPC 2018 (PDF on the project page).
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Simulated Annealing in CUDA

Simulated Annealing in CUDA for floorplanning.
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DSP processor in FPGA

Course project: implementation of a simple DSP processor similar to TI's TMS320C25, in Verilog on FPGA.
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DDS Signal Generator in VHDL

FPGA implementation of a Direct Digital Synthesis signal generator (sine, square, triangle and arbitrary signals) with LUTs.
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Channel Estimation for MIMO-OFDM

Extended SISO channel estimation algorithms to MIMO-OFDM systems.
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Visitor Counter in MATLAB

Published in Electronics For You magazine, Nov 2011.
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CUDA grep

Google RE2 regex search implementation in GPU (CUDA).
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GPU-accelerated LTE simulation

M.S. by Research thesis: GPU acceleration of LTE physical layer simulation.
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Home Automation

Wi-Fi and voice controlled, NLP, custom embedded devices, NodeJS.
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CreaMed

Microsoft Hackathon app: electronic medical records synced to the cloud, reminders for medicines and appointments.